1. Technical Field
The disclosed embodiments relate to phase-locked loops (PLLs).
2. Background Information
Phase-locked loops (PLLs) are used in many applications, including use in local oscillators of cellular telephone receivers and transmitters. FIG. 1 (Prior Art) is a simplified diagram of one such type of PLL 1. This type of PLL may, for example, be used to tune the frequency of a local oscillator (LO) signal, where the LO signal is supplied to a mixer of a receiver in the cellular telephone such that the receiver is tuned to receive a radio signal of interest. PLL 1 includes a phase detector 2, a charge pump 3, a loop filter 4, a voltage-controlled oscillator (VCO) 5, a divider 6, and a delta-sigma modulator 7 (also referred to as a sigma-delta modulator). Divider 6 divides the frequency of the LO signal on node 8 by a multi-bit digital divisor value received on leads 9, and outputs the resulting lower frequency feedback clock signal onto node 10. Delta-sigma modulator 7 varies the multi-bit digital divisor value on leads 9 over time such that the frequency of the LO signal on node 8 divided by the frequency of the feedback clock signal on node 10 is a fractional-N divisor value over time. The fractional-N divisor value can be changed by changing a multi-bit digital frequency control word received onto delta-sigma modulator 7 via leads 11. The frequency of the LO signal on node 8 is adjusted to tune the receiver by adjusting the multi-bit digital frequency control word. Improving the performance of PLLs such as PLL 1 of FIG. 1, and of circuits that contain such PLLs, is desired.